Dynamic Random Access Memory (DRAM) cells include a capacitor for storing charge. The capacitor can be coupled to a transistor (e.g., passive write gate or active write transistor) for transferring charge to and from the capacitor. Reducing the size of the cell is critical to advancing technology nodes. This reduction in size also determines speed, chip density, and cost of manufacture.
In past technologies nodes, cell reduction has been done, normally, by shrinking feature sizes to shrink the cell. However, in addition to shrinking the cell features, an effective way to reduce cell area is to reduce the largest feature in the cell, e.g., the area of the storage capacitor. One way to reduce DRAM cell size without reducing storage capacitance is to use trench capacitors in the cells.
Typically, trench capacitors are formed by etching long deep trenches in a silicon wafer, selectively doping the trench sidewalls, and coating the trench with a dielectric layer. The coated trench is then filled with polysilicon or amorphous silicon to form a vertical cell capacitor plate and, as a result, a cell capacitor on its side in the trench. Thus, the silicon surface “real estate” required for the storage capacitor is dramatically reduced without sacrificing capacitance.
For state of the art trench capacitor DRAM cells, a plate is formed in the sidewall of the trench, by doping the sidewall of the trench. In SOI technology, this doping can damage the sidewalls of the SOI film, which can affect the crystalline structure of the silicon (SOI). This damaged area typically forms the active region of the gate structure, i.e., transistor. Accordingly, due to the damage, the gate will have degraded performance characteristics, which is not desirable.
Accordingly, there exists a need in the art to overcome the deficiencies and limitations described hereinabove.